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toshiba toshiba corporation 1/18 tlcs-90 series TMP90CH44 the information contained here is subject to change without notice. the information contained herein is presented only as guide for the applications of our products. no responsibility is assumed by toshiba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. these toshiba products are intended for usage in general electronic equipments (of?e equipment, communication equipment, measuring equipment, domestic electri?ation, etc.) please make sure that you consult with us before you use these toshiba products in equip- ments which require high quality and/or reliability, and in equipments which could have major impact to the welfare of human life (atomic energy control, spaceship, traf? signal, combustion control, all types of safety devices, etc.). toshiba cannot accept liability to any damage which may occur in case these toshiba products were used in the mentioned equipments without prior consultation with toshiba. cmos 8?it microcontrollers TMP90CH44n/TMP90CH44f 1. outline and characteristics the TMP90CH44 is a high-speed, high performance 8-bit microcontroller developed for application in the control of various devices. TMP90CH44, cmos 8-bit microcontroller, integrates an 8-bit cpu, rom, ram, a/d converter, multi-function timer/event counter, general-purpose serial interface and slave functions in a single chip, and with which external program memory and data memory can be extended up to 48kb. TMP90CH44n is a device with a 64-pin shrink dip. TMP90CH44f is a device with a 64-pin ?t package. the following are the features of TMP90CH44: (1) highly ef?ient instructions: 163 types of basic instructions, including multiplication, division, 16-bit arithmetic operations, bit manipulation instructions (2) minimum instruction executing time: 250ns (at 16mhz oscillation frequency) (3) built-in rom: 16kb (4) built-in ram: 512 bytes (5) memory expansion external program memory: 48kb external data memory: 48kb (6) highly accurate 8-bit a/d converter (4 channels) (7) general-purpose serial interface (1 channel) with asynchronous mode and i/o interface mode (8) multi-function 16-bit timer/event counter (1 channel) (9) 8-bit timer (4 channels) (10) stepping motor control and pattern generation ports (2 channels) (11) input/output ports: 54 pins (12) slave function (13) interrupt function: 12 internal, 3 external (14) micro direct memory access (dma) function (4 channels) (15) watchdog timer function (16) standby function (3 halt modes)
2/18 toshiba corporation TMP90CH44 figure 1. tmp90c844 block diagram
toshiba corporation 3/18 TMP90CH44 2. pin assignment and functions the assignment of input/output pins for tmp90c844, their name and outline functions are described below. 2.1 pin assignment figure 2.1 (1) shows pin assignment of the tmp90c844n. figure 2.1 (1). pin assignment (shrink dip)
4/18 toshiba corporation TMP90CH44 figure 2.1 (2) shows the pin assignment of TMP90CH44f. figure 2.1 (2). pin assignment (flat package)
toshiba corporation 5/18 TMP90CH44 2.2 pin names and functions the names of input/output pins and their functions are summarized in table 2.2. table 2.2 (1/2) pin name no. of pins i/o or tristate function p00 ~ p07 /ad0 ~ ad7 8 i/o port 0: each bit can be set for input or output /tristate address/data bus: operates as an 8-bit bidirectional address bus or data bus when using external memory. p10 ~ p17 /a8 ~ a15 8 i/o port 1: an 8-bit i/o port. each bit can be set for input or output. /output address bus: operates as an address bus (upper 8 bits) when using external memory. p20 ~ p27 /sb0 ~ sb7 /w ait 8 (8) (1) i/o port 2: each bit can be set for input or output. address bus: the upper 8 bits address bus for external memory. /input wait: input pin for connecting a memory or peripheral lsi with delayed access time. p30 ~ p37 8 i/o port 3: 8-bit i/o port which allows i/o selection on bit basis (with programmable pull-up resistor). /swr (1) /input slave write: the strobe signal input to write data from the master processor. /srd (1) /input slave read: the strobe signal used by the master processor to read data. /scs (1) /input slave chip select: the chip select signal input from the master processor. c/d (1) input command/data: the command/data select signal input from the master processor. /st a (1) /output status output: used to report the slave bus status to the master processor. rxd (1) input receiver of serial data /sclk (1) /i/o serial clock /txd (1) /output transmitter of serial data p40 ~ p47 8 i/o port 4: 8-bit i/o port which allows i/o selection on bit basis (with programmable pull-up resistor). /to1, 3, 4, 5 (4) /output timer outputs 1, 3,4, and 5: output ports for timer 0, or timer 1, timer 2, timer 3 and timer 4 (2 lines). /ti0, 2, 4, 5 (4) /input timer inputs 0, 2, 4, and 5: input ports for timer 0, or timer 1, timer 2 and timer 4 (2 lines). /int0 (1) /input interrupt request terminal 0: interrupt request pin 0: level/rise edge programmable interrupt request pin. /int1 (1) /input interrupt request terminal 1: interrupt request pin 1: rise/fall edge programmable interrupt request pin. /int2 (1) /input interrupt request terminal 2: interrupt request pin 2: rise edge interrupt request pin. p50 ~ p53 /an0 ~ an3 4 input port 50 ~ 53: 1-bit output ports. analog input: 4 analog inputs to a/d converter. p56 /rd 1 output port 56: a 1-bit output port. read: strobe signal output for reading external memory.
6/18 toshiba corporation TMP90CH44 table 2.2 (2/2) pin name no. of pins i/o or tristate function p57 /wr 1 output port 57: a 1-bit output port. write: strobe signal output for writing external memory. p60 ~ p63 /m00 ~ m03 4 i/o /output port 6: 4 bit i/o port which allows i/o selection on bit basis. stepping motor control port 0 or pattern generation port 0. p70 ~ p73 /m10 ~ m13 4 i/o output port 7: 4 bit i/o port which allows i/o selection on bit basis. stepping motor control port 0 or pattern generation port 1. ale 1 output address latch enable clk 1 output clock output: generates clock pulse at 1/4 frequency of clock oscillation. it is pulled up internally during resetting. ea 1 input external access: connects with v cc pin in the tmp90c844 built rom is used. reset 1 input reset: initializes the tmp90c844. (pull-up resistance is built-in). x1, x2 2 i/o crystal oscillator connection pin vref 1 input of reference voltage to a/d converter agnd 1 gnd pin for a/d converter v cc 1 power supply (+5v +/- 10%) gnd 1 gnd pin (0v)
toshiba corporation 7/18 TMP90CH44 3. operation the following explains the TMP90CH44 functions and basic operations. the cpu functions and internal i/o functions of the TMP90CH44 are the same as the tmp90c844. refer to the ?mp90c844?section concerning functions which are not explained in the following. 3.1 cpu the TMP90CH44 has an internal high performance 8-bit cpu. refer to the book tlcs 90 series cpu core architecture section concerning the cpu operation. 3.2 memory map the TMP90CH44 can provide a maximum 48k byte program and data memory. the program and data memories may be allocated to the address 0000h ~ ffffh. (1) built-in rom the TMP90CH44 has an internal 16k-byte rom. this rom is located at addresses 0000h ~ 3fffh. program execution s tarts from address 0000h after a reset operation. addresses 0008h ~ 0078h in the internal rom area are used as the interrupt processing entry area. (2) built-in ram the mp90ch44 contains a 512-byte built-in ram which is allocated to the addresses ffc0h ~ ffbfh. the cpu can also access some portions of the ram (192 byte area ff00h ~ ffbfh) using short instruction codes in the direct addressing mode. addresses of ff18h ~ ff78h this ram area can be used as the parameter area for micro dma process- ing. (this area can freely be used when the micro dma function is not used.) (3) built-in i/o the TMP90CH44 uses 56 bytes of the address space as a built-in i/o area. the area is allocated to the addresses ffc0h ~ fff7h. the cpu can access the built-in i/o using short instruction codes in the direct address ing mode. figure 3.2 shows the memory map and the access ranges of the cpu for each addressing mode.
8/18 toshiba corporation TMP90CH44 figure 3.2. memory map
toshiba corporation 9/18 TMP90CH44 4. electrical characteristics TMP90CH44n/TMP90CH44f 4.1 absolute maximum ratings symbol parameter rating unit v cc power supply voltage -0.5 ~ + 7 v v in input voltage -0.5 ~ v cc + 0.5 v p d power dissipation (ta = 85 c) f 500 mw n 600 t solder soldering temperature (10s) 260 c t stg storage temperature -65 ~ 150 c t opr operating temperature -40 ~ 85 c 4.2 dc characteristics v cc = 5v 10% ta = -20 ~ 70 c (1 ~ 16mhz) typical values are for ta = 25 c and vcc = 5v. symbol parameter min max unit test conditions v il input low voltage (p0) -0.3 0.8 v v il1 p1, p2, p3, p4, p5, p6, p7 -0.3 0.3v cc v v il2 reset , p45 (into) -0.3 0.25v cc v v il3 ea -0.3 0.3 v v il4 x1 -0.3 0.2v cc v v ih input high voltage (p0) 2.2 v cc + 0.3 v v ih1 p1, p2, p3, p4, p5, p6, p7 0.7v cc v cc + 0.3 v v ih2 reset , p45 (into) 0.75v cc v cc + 0.3 v v ih3 ea v cc - 0.3 v cc + 0.3 v v ih4 x1 0.8v cc v cc + 0.3 v v ol output low voltage 0.45 v i ol = 1.6ma v oh v oh1 v oh2 output high voltage 2.4 0.75v cc 0.9v cc v v v i oh = -400 m a i oh = -100 m a i oh = -20 m a i dar darlington drive current (8 i/o pins) (note) -0.1 -3.5 ma v ext = 1.5v r ext = 1.1k w i li input leakage current 0.02 (typ) 5 m a 0.0 vin v cc i lo output leakage current 0.05 (typ) 10 m a 0.2 vin v cc - 0.2 i cc operating current (run) idle 1 35 (typ) 1.5 (typ) 50 5 ma ma tosc = 16mhz stop (ta = -20 ~ 70 c) stop (ta = 0 ~ 50 c) 0.2 (typ) 40 10 m a m a 0.2 vin v cc - 0.2 v stop power down voltage (@stop) 2.0 6.0 v v il2 = 0.2v cc , v ih2 = 0.8v cc r rst reset pull up register 50 150 k w cio pin capacitance 10 pf testfreq = 1mhz v th schmitt width reset , p45) 0.4 1.0 (typ) v
10/18 toshiba corporation TMP90CH44 ac measuring conditions output level: high 2.2v/low 0.8v, c l = 50pf (however, cl = 100pf for ad0 ~ 7, a8 ~ 15, ale, rd , wr ) input level: high 2.4v/low 0.45v (ad0 ~ ad7) high 0.8v cc /low 0.2v cc (excluding ad0 ~ ad7) 4.3 ac characteristics v cc = 5v 10% ta = -20 ~ 70 c (1 ~ 16mhz) symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t osc oscillation cycle ( = x) 80 1000 80 62.5 ns t cyc clk period 4x 4x 320 250 ns t wh clk high width 2x - 40 120 85 ns t wl clk low width 2x - 40 120 85 ns t al a0 ~ 7 effective address ? ale fall 0.5x - 15 25 16 ns t la ale fall ? a0 ~ 7 hold 0.5x - 15 25 16 ns t ll ale pulse width x - 40 40 23 ns t lc ale fall rd /wr fall 0.5x - 30 10 1 ns t cl rd /wr ? ale rise 0.5x - 20 20 11 ns t acl a0 ~ 7 effective address ? rd /wr fall x - 25 55 38 ns t ach upper effective address ? rd /wr fall 1.5x - 50 70 44 ns t ca rd /wr fall ? upper address hold 0.5x - 20 20 11 ns t adl a0 ~ 7 effective address ? effective data input 3.0x - 35 205 153 ns t adh upper effective address ? effective data input 3.5x - 55 225 164 164 ns t rd rd fall ? effective data input 2.0x - 50 110 75 ns t rr rd pulse width 2.0x - 40 120 85 ns t hr rd rise ? data hold 0 0?ns t rae rd rise ? address enable x - 15 65 48 ns t ww wr pulse width 2.0x - 40 120 85 ns t dw effective data ? wr rise 2.0x - 50 110 75 ns t wd wr rise ? effective data hold 0.5x - 10 30 21 ns t ackh upper address ? clk fall 2.5x - 50 150 106 ns t ackl lower address ? clk fall 2.0x - 50 110 75 ns t ckha clk fall ? upper address hold 1.5x - 80 40 13 ns t cck rd /wr ? clk fall x - 25 55 37 ns t ckhc clk fall ? rd /wr rise x - 60 20 2 ns t dck valid data clk fall x - 50 30 12 ns t cwa rd /wr fall ? valid wait x - 40 40 22 ns t awal lower address ? valid wait 2.0x - 70 90 55 ns t wah clk fall ? valid wait hold 0 0?ns t awah upper address ? valid wait 2.5x - 70 130 86 ns t cpw clk fall ? port data output x + 200 280 262 ns t prc port data input ? clk fall 200 200 200 ns t cpr clk fall ? port data hold 100 100 100 ns
toshiba corporation 11/18 TMP90CH44 4.4 a/d conversion characteristics v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter condition min max unit v ref analog reference voltage vcc - 1.5 vcc vcc v a gnd analog reference voltage vss vss vss v ain analog input voltage range vss vcc iref supply current for analog reference voltage 0.5 1.0 ma error (quantize error of 0.5 lsb not included) total error (ta = 25 c, vcc = v ref = 5.0v) 1.0 lsb total error 2.5 4.5 zero-cross characteristics v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter condition min max unit v zx zero-cross detection input ac coupling c = 0.1 m f 1 1.8 v ac p - p a zx zero-cross accuracy 50/60hz sine wave 135 mv f zx zero-cross detection input frequency 0.04 1 khz 4.6 timer/ counter input clock (ti0, ti2, and ti4) v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t vck clock cycle 8x + 100 740 600 ns t vckl low clock pulse width 4x + 40 360 290 ns t vckh high clock pulse width 4x + 40 360 290 ns 4.7 interrupt operation v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t intal int0 low level pulse width 4x 320 250 ns t intah int0 high level pulse width 4x 320 250 ns t intbl int1, int2 low level pulse width 8x + 100 740 600 ns t intbh int1, int2 high level pulse width 8x + 100 740 600 ns
12/18 toshiba corporation TMP90CH44 (2) sclk output mode 4.8 serial channel timing - i/o interface mode (1) sclk input mode v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t scy sclk cycle 16x 1.28 1 m s t oss output data ? rising edge of sclk t scy /2 - 5x - 50 190 137 ns t ohs sclk rising edge ? output data hold 5x - 100 300 212 ns t hsr sclk rising edge ? input data hold 0 0?ns t srd sclk rising edge ? effective data input t scy - 5x -5 0 780 587 ns symbol parameter variable 12.5mhz clock 16mhz clock unit min max min max min max t scy sclk cycle (programmable) 16x 8192x 1.28 655.4 1 512 m s t oss output data ? sclk rising edge t scy - 2x - 50 970 725 ns t ohs sclk rising edge ? output data hold 2x - 80 80 45 ns t hsr sclk rising edge ? input data hold 0 0?ns t srd sclk rising edge ? effective data input t scy - 2x - 150 970 725 ns 4.9 slave bus interface timing: rd , wr bus mode v cc = 5v 10% ta = -20 ~ 70 c f = 1 ~ 16mhz symbol parameter min max unit t sar c/d setup ? srd fall 20 ns t hra srd rise ? c /d hold 5 ns t scr scs setup ? srd fall 0 ns t hrc srd rise ? scs hold 0 ns t wrd srd pulse width 120 ns t ard srd fall ? effective data output 80 ns t vrb srd rise ? effective data hold 10 85 ns t saw c/d setup ? swr fall 20 ns t hwa swr rise ? c /d hold 5 ns t scw scr setup ? swr fall 0 ns t hwc swr rise ? scs hold 0 ns t wwr swr pulse width 120 ns t sbw effective data input ? swr rise 80 ns t hwb swr rise ? effective data hold 10 ns
toshiba corporation 13/18 TMP90CH44 slave bus interface timing: ds , r/w bus mode symbol parameter min max unit t sad c/d setup ? ds fall 20 ns t hda ds rise ? c /d hold 5 ns t scd scs setup ? ds fall 0 ns t hdc ds rise ? scs hold 0 ns t sad scs setup ? ds fall 20 ns t hda ds rise ? r/w hold 5 ns t wds ds pulse width 120 ns t ads ds fall ? effective data output 80 ns t vdb ds rise ? effective data hold 10 85 ns t sbd effective data input ? ds rise 80 ns t hdb ds rise ? effective data hold 10 ns st a change timing x = 1/fosc symbol parameter variable 16mhz clock unit min max min max t rph sta fall after output buffer is read 2x + 50 175 ns t wph sta rise after input buffer is written 2x + 50 175 ns
14/18 toshiba corporation TMP90CH44 4.10 timing chart
toshiba corporation 15/18 TMP90CH44 4.11 timing chart for i/o interface mode 4.12 timing chart for slave bus interface: rd , wr bus mode (1) read operation
16/18 toshiba corporation TMP90CH44 (2) write operation
toshiba corporation 17/18 TMP90CH44 4.13 timing chart for slave bus interface: ds , r/w bus mode (1) read operation
18/18 toshiba corporation TMP90CH44 (2) write operation

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